library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity testframe is
	Port ( 	clk : in  STD_LOGIC;
			
			fifo_empty : in std_logic;
			
			-- outgoing
			data_valid : out std_logic;
			data : out unsigned(7 downto 0)
		);		 
end testframe;

		

architecture Behavioral of testframe is
	

	signal state : unsigned(2 downto 0) := "000";
	
	signal seq_nr : unsigned(15 downto 0) := (others => '0');
	
begin


	
	process (clk)
	begin
		if rising_edge(clk) then
		
			case state is 
			
				when "000" =>
					if fifo_empty='1' then
						state <= "001";
					end if;
				
				when "001" =>	
					state <= "010";
				
				when "010" =>	
					state <= "011";
					
				when "011" =>	
					state <= "100";
					
				when "100" =>	
					state <= "101";
				
				when "101" =>	
					state <= "000";
					seq_nr<=seq_nr+1;
					
				when others =>
					state <= "000";

			end case;
			
		end if;
	end process;
	
	
	data_valid <= '1' when state>0 else '0';
	with state select data <= 
			"00000001" when "001",
			"00000010" when "010",
			"00000011" when "011",
			seq_nr(15 downto 8) when "100",
			seq_nr(7 downto 0) when others;
	

end Behavioral;





